PESTO℠ ESD/EOS simulation: How does it work?

The PESTO℠ service provides a simplified online interface to a full-featured hybridized SPICE simulation of basic ESD/EOS protection devices interacting with basic circuit board parasitics and the devices they are intended to protect.

SPICE-based simulations typically assume that the circuit will remain "functional" during a transient analysis. The nature of ESD and EOS suggests that normal operating conditions of the devices will be exceeded during the analysis, and this means that dynamic response of devices is not only modulated by currents, voltages and time, but that the devices change their response based on recent abuse. What happens when the devices are taken far beyond their operating boundaries for short periods of time is a critical consideration. Sometimes it is sufficent to know that one or more devices have failed, and that is that. In some cases, it is interesting to know if a device will "fail open" or "fail short" and though damaged and more vulnerable, if the interface may still operate after the destruction.

First order protection circuit design analysis is often based on datasheet parameters of Transient Voltage Suppressors (TVS) devices, such as ESD Rating (VESD, IEC61000-4-2 robustness rating, etc), and Clamping Voltage (VCLAMP),etc. These parameters are usually tested under the one condition which they will never see in a circuit: by themselves!

Since TVS devices (the Device Under Test) are always included in a circuit to divert strike energy away from the Device Under Protection (DUP), the actual Clamping Voltages at the two devices are distinct and the voltage at the protected device (VDUP) during a strike is not Zero. The current diverted by the DUT (ISHUNT) is not 100%, and the residual current into the protected device (IRESIDUAL) is also not 0%.

Second Order modeling of this interaction comprehends the KCL current division between these two dynamic devices, and the current, voltage, power and energy maximum limits which can cause latent or permanent damage in either the DUT or DUP (or even the PCB traces themselves if the pulses are sufficiently energetic.) Most device IBIS or SPICE models available today provide information about "clamping devices" in device I/O's, but these elements were intended to model signal integrity issues like overshoot and ringing within 5-10% above and below VDD and VSS. ESD/EOS strikes inject levels 1000x or more what are contemplated in those models, and while simulators will happily extrapolate those models out to +/- 50Amps peak for a 4mA clamp, there is no information on when the device will fail and how it will behave on the way there and beyond.

Given meaningful device models in the ESD/EOS regime, this level of approximation provides superior estimations of the system level robustness for a given conducted pulse applied to a given node for the specific devices. However, it does not typically address soft errors, system upsets, secondary discharges or coupled pulses into adjacent conductors and devices.

Third order modeling attempts to virtualize the entire 3D system assembly and solve the aggressor E- and B-field interactions predicted by Maxwell's equations. Given the exorbitant amount of accurate physical and electrical model input required, this can theoretically provide the most complete and accurate representation of an ESD/EOS strike on a system. It is also extremely difficult and time consuming. While elegant and expensive 3D field-solvers are commercially available and extremely powerful, given the dearth of accurate ESD-regime electrical models for devices, they can also produce prodigious amounts of "Garbage-In, Garbage-Out."

For most quantitative "compare and contrast" analysis, though, the second order analysis with accurate models can provide excellent results for "better or worse" analysis.

But no simulation under any circumstance should be assumed to answer all questions, nor be extrapolated outside its limited sphere of valid inputs. The pass/fail criteria of a system are defined at the system level. For example, one TVS device may clamp harder and faster than another device. This additional shunt current may inject undesirable currents and risetimes into power rails or ground, causing secondary upsets on other devices. Assumptions outside the scope of any limited simulation are not necessarily valid.