Littelfuse selects PESTO[SM] modeling technology for iDesign™ Portal

Littelfuse has embraced the "SEED" (System Efficient ESD Design) Concept promoted by the Industry Council on ESD Target Levels and in academic publications from the EOS/ESD Association.

Read Press Release here.

This design methodology requires device models accurate in high-speed/high-current levels far beyond the range of typical IBIS or SPICE models supplied by vendors for signal integrity modeling.

Littelfuse's iDesign™ portal allows users to quickly select and run validated models for their extensive TVS catalog against user supplied ASIC specifications in order to better predict which TVS device is best suited for the designer's system level robustness goals.

For a more detailed report on the protection of specific ASIC I/O characteristics, or for more complex circuit topologies and analysis, Pragma Design can create custom device models, run simulations and provide complete and custom design guides for best robustness results in a particular design engineer's newest project. For a troublesome legacy design, Pragma can help the sustaining engineer or procurement manager find a truly suitable replacement part.

These custom models can be added to individual and confidential designer accounts within PESTO℠, so that team members can collaborate on various combinations of TVS and ASIC options without divulging performance or BOM lists to competitors through an open-ended online simulation utility.

Try the Littelfuse iDesign™ ESD selection tool here.

Read more about PESTO℠ and advanced ESD Analysis consulting services from Pragma here.

Contact Pragma and find out how we can help you create a PESTO™ account and library for further evaluation.